Split gate non-volatile flash memory cells having a select gate, a floating gate, a control gate and an erase gate are well known in the art. See for example U.S. Pat. Nos. 6,747,310, 7,868,375 and 7,927,994, and published application 2011/0127599, which are all incorporated herein by reference in their entirety for all purposes. Such split gate memory cells include a channel region in the substrate that extends between the source and drain. The channel region has a first portion underneath the floating gate (hereinafter called the FG channel, the conductivity of which is controlled by the floating gate), and a second portion underneath the select gate (hereinafter the WL channel, the conductivity of which is controlled by the select gate).
In order to increase read performance, the thickness of the oxide layer under the select gate is minimized. However, reducing this oxide layer thickness needs to be accompanied by an increase in P-type doping in the select gate channel region, in order to maintain desired target word line threshold voltage. One solution may be to implant a P-type dopant into the WL channel portion of the channel region (under the select gate). This could be done by performing a P-type implant step after the floating gate and control gate have been formed but before the select gate is formed, so that only the WL channel portion of the channel region will receive the increased doping by the implant step.
However, during subsequent thermal cycles, dopant implanted into the WL channel inevitably diffuses laterally into the FG channel, causing a local increase in the FG transistor threshold on the side closest to the select gate. FIG. 1 illustrates one example of P-type dopant distribution within a split gate cell. As seen in FIG. 1, the dopant distribution in the FG channel (underneath the floating gate) is not uniform, which is undesirable because it can make it more difficult to turn on the heavily doped portion of the FG channel and to turn off the lightly doped portion of the FG channel.